sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<bjdooks> sheesh, looks like sifive_u qemu's mmc-spi hasn't been working for ages due to a qemu bug or two
<dramforever[m]1> shadows: one of my colleagues also couldn't get it to work on the orangepi rv, same problem
<dramforever[m]1> so it's not just you
<shadows> dramforever[m]1: that's helpful to know, thanks. I've submitted a series to add Mars CM (and Mars CM Lite) to Linux kernel upstream.
<bjdooks> I should get another revision of my big-endian patch series sorted
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<la_mettrie> it's been said that Star64 has another PCIE controller disabled in the device tree because it uses USBPHY instead of PCIE-USB bridge. But is this difference purely at the level of device tree or does it reflect differences in hardware (Star64 vs. VisionFive2)?
<dramforever[m]1> la_mettrie: chip is the same, board is different
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<bjdooks> sheesh, and cmd13 fixed
<bjdooks> three days of pissing about with stuff and the result is like 4 lines of diff
<aurel32> it seems that glibc test tst-socket-timestamp is broken with kernel 6.16 (works fine with 6.15). I haven't investigated why yet, has someone an idea or already started looking at that?
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<shadows> la_mettrie: I do not know what happens on VisionFive2 if you try to use its USBPHY as a host port, but it does have that connection to the USB-C power input port
<shadows> la_mettrie: there is also a USB overcurrent register on JH7110 that needs to be written to, which is done in upstream U-Boot (not done in Linux)
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<aurel32> found the issue with tst-socket-timestamp, __put_user_nocheck got broken in 6.16-rc1, preparing a patch
<dramforever[m]1> oh no
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<aurel32> patch sent
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